Wednesday, July 8, 2020

Chromite-M SoC targeted for FPGAs

Today, InCore announces the availability of its open source Chromite-M SoC  targeted for FPGAs. The Chromite-M SoCis a minimal SoC that uses an RV64IMAC core generated from the Chromite Core  Generator. This SoC is the first member of a family open-source reference SoCs from InCore. 

This release  is targeted at the Digilent Arty-100 FPGA board and is accompanied by an SDK from Zephyr OS. The open source community finally has a production ready open source Core, Interconnect and SoC with extensive documentation. 

The Chromite-M SoC, is targeted for high-performance RTOS based embedded applications like networking, storage controllers, wearables, IoT aggregation. The Chromite core in the SoC has the following configuration:  
  • Supports RV64IMACU and compliant with the latest version of the Unprivileged and Privileged ISA specifications. 
  • Machine and User mode support. 
  • 16KiB 4-way set-associative Instruction Cache. 
  • 16KiB 4-way set-associative Data Cache. 
  • Gshare based branch predictor with a 512-entry Branch History Table (BHT) and 32-entry Branch Target Buffer (BTB) 
  • An 8-entry Return Address Stack (RAS). 
  • 2-cycle integer multiplier, and a 64-cycle integer divider unit. 
  • Physical memory protection of up to 4 regions with a granularity of 8-bytes 
  • AXI-4 compliant master interfaces for the I-cache and D-cache. 
  • A debugger with JTAG interface. 
The SoC includes the following open-source devices and interconnect IPs: 
  • PLIC: A Platform Level Interrupt Controller with 17 interrupts and 3 levels of priority. 
  • GPIOs: up to 16 configurable General Purpose IOs are available. 
  • UART: A simple interrupt-driven UART controller. 
  • CLINT: Core Local Interrupt Controller for timer and soft-interrupts. 
  • On-Chip Memory: a 16KiB BRAM. 
  • BootROM: A 4KiB boot ROM memory based on BRAMs. 
  • 64-bit AXI-4 compliant Crossbar: This cross-bar connects the cache masters, debug master, high speed peripherals (like DDR) and bridges to slow peripherals. 
  • AXI4-to-APB and AXI4-to-AXI4-Lite bridges. 
  • An AXI4 open-slave to connect third part IPs. 
The above seof device and interconnect IPs are completely open source, and are available under a permissive open source license on Gitlab by InCoreAn attractive feature of the device IPs is that they are extremely configurable and include an abstract device-configuration wrapper which allows these devices to be mapped to almost any interconnect protocol seamlessly.  

The SoC also depends on external IPs for the following: 
  • DDRx Xilinx DDR IP controlle 
  • JTAG: Xilinx BSCANE2 JTAG TAP cell for remote host debugging. While an open-source JTAG controller is available from InCore, using the BSCANE2 re-uses the same micro-usb interface for debugging and programming FPGA. 

While the SoC itself is designed to be FPGA independent, the current release supports the Arty-100t FPGA board (from Digilent) which has an Artix-7 series FPGA. On this FPGA, while the core currently runs at 50MHz the entire SoC consumes less than 70% of the LUTs availableInCore plans to support other standard FPGA boards for the same SoC depending on interest from the community. 

InCore is continuously working on enhancing the SoC with other common peripherals like I2C, SPI, QSPI, Watchdog timers and PWMs, as part of its future releases  

The SoC also comes along with a full featured Zephyr port supporting the current feature set. Zephyr Shell applications can be run on the Chromite M SoC on the Arty board. 

The Chromite M Soc also includes an extensive documentation of the devices, cores and SoC which will allow SW developers to create new OS ports and build applications on the platform. . 

By contributing code to the open-source community, InCore aims at not only democratizing silicon development, but also encourage open-source contributions to both HW and SW ecosystems.

Detailed steps for building and using the Chromite-M SoC can be found here: 


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  2. what is the methodology of chromite m soc